1. Field of the Invention
The present invention relates to a semiconductor measurement and analysis technology. More particularly, the present invention relates to a method of fabricating sample lamella for transmission electron microscopy (TEM) analysis.
2. Description of Related Art
During the failure analysis and the process evaluation of VLSI (very large scale integration) device, cross-section analysis is considered as an effective technology. The scanning electron microscopy (SEM) is a tool for observing the cross-section, but the resolution is relatively weak for the high-density device. Therefore, when the semiconductor process progresses into the stage of VLSI, SEM are gradually replaced by TEMs. The TEMs are widely used in the failure analysis and process evaluation, so as to solve the problem concerning output and device reliability.
Generally speaking, in the TEM analysis technology, the fabrication of the sample lamella is one of the crucial steps. When a TEM is used for observing, the thickness of the sample membrane must be smaller than 0.1 μm, so as to provide the transmittance required by the electron transmission of TEM and to acquire clear images. Recently, the fabrication of the sample membrane for TEM analysis at a specific position must use a focused ion beam (FIB) thinning technology to perform a sample membrane thinning process, and in order to prevent the surface of a chip from being damaged by an ion beam, usually a Pt film (or a W film) is formed on the surface of the chip to block sputtering by the ion beam.
In another aspect, although the Pt film (or W film) can prevent the surface of the chip from being damaged by the ion beam, usually the Pt film (W film) is also formed by using an FIB depositing technology. In this method, when the Pt film (or W film) is formed, a damage layer is formed on the chip resulting in the damage of the defect structure to the chip, and thus the analysis of the defect is affected. Although an E-beam can be used to replace the FIB to perform the Pt film (or W film) deposition process, the method may also damage the top layer. Another prior art proposes forming a buffer layer on the chip, and then forming the Pt film (W film) on the buffer layer. However, it is difficult to locate when searching for the defects on the chip.
Therefore, it has become a problem to be solved in the industry as to how to easily fabricate the sample lamella for TEM analysis without damaging the defects on the chip.